1. Field of the Invention
The present invention relates to the field of semiconductor fabrication and, more particularly, to a method for fabricating trench isolation structures.
2. Description of the Prior Art
During the fabrication of semiconductor devices such as shallow trench isolation (STI) structures, high-temperature thermal processes are ordinarily carried out in order to form thermally grown dielectric films or to repair surface damages. As device dimension shrinks to very deep sub-micron scale or beyond, silicon surface defects such as dislocation or slipping becomes a critical issue that might adversely affect device performance.
FIG. 1 to FIG. 5 are schematic, cross-sectional diagrams demonstrating a typical trench isolation process. As shown in FIG. 1, a pad oxide layer 12 and a pad nitride layer 14 are sequentially formed on a front surface 100 of a semiconductor substrate 10. The pad oxide layer 12 is a thermally grown film, while the pad nitride layer 14 is formed by chemical vapor deposition methods. Simultaneously, a silicon oxide layer 22 and a silicon nitride layer 24 are formed on the backside 200 of the semiconductor substrate 10.
As shown in FIG. 2, using the pad nitride layer 14 as an etching hard mask, a lithographic process and an etching process are carried out to etch a trench 30 into the selected area of the front surface 100 of the semiconductor substrate 10.
As shown in FIG. 3, subsequently, an oxidation process is carried out to form a liner oxide layer 40 on interior surface of the trench 30.
As shown in FIG. 4, a high-density plasma chemical vapor deposition (HDP CVD) process is performed to deposit a high-density plasma silicon oxide film 50 over the substrate and into the trench 30. As known in the art, in order to provide better isolation, the high-density plasma silicon oxide film 50 is then subjected to a densification process under an inert environment. Another purpose of this densification process is to repair the damaged silicon surface due to the etching plasma.
As shown in FIG. 5, using the pad nitride layer 14 as a polish stop, a chemical mechanical polishing (CMP) process is then conducted to planarize the high-density plasma silicon oxide film 50.
The above-described prior art method has several drawbacks. First, during the densification process, the silicon nitride layer 24 on the backside 200 of the semiconductor substrate 10 peels off and becomes a potential source of particle contamination, which affects the subsequent lithographic processes. Secondly, it is often desired to apply higher temperatures during the densification process because higher temperatures can repair the damaged silicon surface in a more efficient manner. However, dislocation or slipping defects occur due to the use of higher temperatures.